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cy14b104k, cy14b104m 4-mbit (512 k 8/256 k 16) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07103 rev. *u revised july 12, 2011 4-mbit (512 k 8/256 k 16) nvsram with real time clock features 25 ns and 45 ns access times internally organized as 512 k 8 (cy14b104k) or 256 k 16 (cy14b104m) hands off automatic store on power-down with only a small capacitor store to quantumtrap non-volatile elements is initiated by software, device pin, or autostore on power-down recall to sram is initiated by software or power-up high reliability infinite read, write, and recall cycles 1 million store cycles to quantumtrap 20 year data retention single 3 v +20%, ?10% operation data integrity of cypress nvsram combined with full-featured real time clock (rtc) watchdog timer clock alarm with programmable interrupts capacitor or battery backup for rtc industrial temperature 44-pin and 54-pin thin small outline package (tsop) type ii pb-free and restriction of hazardous substances (rohs) compliant functional description the cypress cy14b104k and cy14b104m combines a 4-mbit non-volatile static ram (nvsram) with a full-featured rtc in a monolithic integrated circuit. the embedded non-volatile elements incorporate quantumtrap technology producing the world?s most reliable non-volatile memory. the sram is read and written infinite number of times, while independent non-volatile data resides in the non-volatile elements. the rtc function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for periodic minutes, hours, days, or months alarms. there is also a programmable watchdog timer for process control. static ram array 2048 x 2048 r o w d e c o d e r column i/o column dec i n p u t b u f f e r s power control store/recall control quatrum trap 2048 x 2048 store recall v cc v ca p hsb a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 software detect a 14 - a 2 oe ce we bhe ble a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 17 a 18 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 rtc mux a 18 - a 0 x out x in int v rtcbat v rtccap logic block diagram [1, 2, 3] notes 1. address a 0 ?a 18 for 8 configuration and address a 0 ?a 17 for 16 configuration. 2. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 3. bhe and ble are applicable for 16 configuration only. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 2 of 35 contents pin definitions .................................................................. 3 device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 autostore operation ........................................................ 4 hardware store (hsb) operation ................................. 5 hardware recall (power-up) ....................................... 5 software store ............................................................... 5 software recall ............................................................. 5 preventing autostore ....................................................... 6 data protection ................................................................. 7 noise considerations ....................................................... 7 real time clock operation .............................................. 7 nvtime operation ....................................................... 7 clock operations ......................................................... 7 reading the clock ....................................................... 7 setting the clock ......................................................... 7 backup power ............................................................. 7 stopping and starting the osc illator ........... ........... ...... 8 calibrating the clock ................................................... 8 alarm ........................................................................... 8 watchdog timer ....... .............. .............. .............. ......... 8 power monitor ............................................................. 9 interrupts ..................................................................... 9 flags register ........................................................... 10 best practices ................................................................. 15 maximum ratings ........................................................... 16 operating range ............................................................. 16 dc electrical characteristics ........................................ 16 data retention and endurance ..................................... 17 capacitance .................................................................... 17 thermal resistance ........................................................ 17 ac test loads ................................................................ 17 ac test conditions ........................................................ 17 rtc characteristics ....................................................... 18 ac switching characteristics ....................................... 19 sram read cycle .................................................... 19 sram write cycle ..................................................... 19 autostore/power-up recall ....................................... 22 switching waveforms .................................................... 22 software controlled store and recall cycle ........ 23 hardware store cycle ................................................. 24 truth table for sram operations ................................ 25 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 package diagrams .......................................................... 27 acronyms ........................................................................ 29 document conventions ......... .................................... 29 units of measure ....................................................... 29 document history page ................................................. 30 sales, solutions, and legal information ...................... 35 worldwide sales and design s upport ......... .............. 35 products .................................................................... 35 psoc solutions ......................................................... 35 [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 3 of 35 pinouts figure 1. pin diagram ? 44-pin and 54-pin tsop ii pin definitions pin name i/o type description a 0 ? a 18 input address inputs. used to select one of the 524,288 bytes of the nvsram for 8 configuration. a 0 ? a 17 address inputs. used to select one of the 262,144 words of the nvsram for 16 configuration. dq 0 ? dq 7 input/output bidirectional data i/o lines for 8 configuratio n. used as input or output lines depending on operation. dq 0 ? dq 15 bidirectional data i/o lines for 16 configuration. used as input or output lines depending on operation. nc no connect no connects. this pi n is not connected to the die. we input write enable input, active low. when selected low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. bhe input byte high enable, active low. controls dq 15 ?dq 8 . ble input byte low enable, active low. controls dq 7 ?dq 0 . x out output crystal connection. drives crystal on startup. x in input crystal connection. for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage. left unconnected if v rtcbat is used. v rtcbat power supply battery supplied backup rtc supply voltage. left unconnected if v rtccap is used. int output interrupt output. programmable to respond to the cl ock alarm, the watchdog timer, and the power monitor. also programmable to either active high (push or pull) or low (open drain). nc a 8 x in x out v ss dq 6 dq5 dq4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin tsop ii top view (not to scale) a 10 v rtcbat we dq 7 hsb int v ss v cc v cap v rtccap (x 8) dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54-pin tsop ii top view (not to scale) oe ce v cc int v ss nc a 9 nc nc 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 (x 16) v rtccap v rtcbat x in x out [4] [4] [5] [5] a 17 a 18 a 16 a 17 notes 4. address expansion for 8-mbit. nc pin not connected to die. 5. address expansion for 16-mbit. nc pin not connected to die. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 4 of 35 device operation the cy14b104k/cy14b104m nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a non-volatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the non-volatile cell (the store operation), or from the non-volatile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b104k/cy14b104m supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the non-volatile cells and up to 1 million store operations. see truth table for sram operations on page 25 for a complete description of read and write modes. sram read the cy14b104k/cy14b104m performs a read cycle when ce and oe are low, and we and hsb are high. the address specified on pins a 0?18 or a 0?17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit word s. when the read is initiated by an address transition, the output s are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common i/o pins do 0?15 are written into the memory if it is valid t sd before the end of a we controlled write or before the end of an ce controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit wo rds. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104k/cy14b104m stores data to the nvsram using one of three storage operations . these three operations are: hardware store, activated by the hsb ; software store, activated by an address sequence; autostore, on device power-down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b104k/cy14b104m. during a normal operation, t he device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 6 . in case autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in nvsram. figure 2. autostore mode figure 2 on page 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 16 for the size of the v cap . the voltage on the v cap pin is driven to v cc by a regulator on the v ss ground ground for th e device. must be connect ed to ground of the system. v cc power supply power supply inputs to the device. 3.0 v +20%, ?10% hsb input/output hardware store busy (hsb ). when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a non-volatile store operation. after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keep s this pin high (external pull-up resistor connection optional). v cap power supply autostore capacitor. supp lies power to the nvsram during power loss to store data from sram to non-volatile elements. pin definitions (continued) pin name i/o type description 0.1 uf v cc 10 kohm v cap we v cap v ss v cc [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 5 of 35 chip. a pull-up should be placed on we to hold it inactive during power-up. this pull-up is effective only if the we signal is tristate during power-up. many mpus tris tate their controls on power-up. this should be verified when using the pull-up. when the nvsram comes out of power-on-recall, the mpu must be active or the we held inactive until th e mpu comes out of reset. to reduce unnecessary non-volatile stores, autostore, and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initia ted store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the system to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b104k/cy14b104m provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the cy14b104k/cy14b104m conditionally initiates a store operation after t delay . an actual store cycle begins only if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) t hat is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14b104k/cy14b104m. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, rega rdless of how it is initiated, the cy14b104k/cy14b104m c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power-up or after any low power condition (v cc cy14b104k, cy14b104m document #: 001-07103 rev. *u page 6 of 35 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power-down cycles. the part comes from the factory with autostore enabled. table 1. mode selection ce we oe bhe , ble [6] a 15 ?a 0 [7] mode i/o power h x x x x not selected output high z standby l h l l x read sram output data active l l x l x write sram input data active l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [8] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [8] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram non-volatile store output data output data output data output data output data output high z active i cc2 [8] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram non-volatile recall output data output data output data output data output data output high z active [8] notes 6. bhe and ble are applicable for 16 configuration only. 7. while there are 19 address lines on the cy14b104k (18 a ddress lines on the cy14b104m), only 13 address lines (a 14 ?a 2 ) are used to control software modes. the remaining address lines are don?t care. 8. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a non-volatile cycle. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 7 of 35 data protection the cy14b104k/cy14b104m prot ects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low-voltage condition is detected when v cc is less than v switch . if the cy14b104k/cy14b104m is in a write mode (both ce and we are low) at power-up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against i nadvertent writes during power-up or brown out conditions. noise considerations refer to cy application note an1064 . real time clock operation nvtime operation the cy14b104k/cy14b104m offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. rtc registers use the last 16 address locations of the sram. internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write oper ation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. rtc functionality is described with respect to cy14b104k in the following sections. the same description applies to cy14b104m, except for the rtc register addresses. the rtc register addresses for cy14b104k range from 0x7fff0 to 0x7ffff, while those for cy14b104m range from 0x3fff0 to 0x3ffff. refer to table 3 on page 11 and table 4 on page 12 for a detailed register map description. clock operations the clock registers maintain time up to 9,999 years in one second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. the user must stop internal updates to the cy14b104k time keeping registers before reading clock data, to prev ent reading of data in transition. stopping the register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x7fff0), and does not restart until a ?0? is written to the read bit. the rtc registers are then read while the internal clock continues to run. after a ?0? is written to the read bit (?r?), all rtc registers are simultaneously updated within 20 ms. setting the clock setting the write bit ?w? (in the flag s register at 0x7fff0) to a ?1? stops updates to the time keeping registers and enables the time to be set. the correct day, date, and time is then written into the registers and must be in 24 hour bcd format. the time written is referred to as the ?base time?. th is value is stored in non-volatile registers and used in the calculation of the current time. resetting the write bit to ?0? transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. if the time written to the timekeeping registers is not in the correct bcd format, each invalid nibble of the rtc registers continue counting to 0xf before rolling over to 0x0 after which rtc resumes normal operation. note after ?w? bit is set to 0, values written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the rtc time keeping counters in t rtcp time. these counter values must be saved to non-volatile memory either by initiating a software/hardware store or autostore operation. while working in autostore disabled mode, perform a store operation after t rtcp time while writing into the rtc registers for the modifications to be correctly recorded. backup power the rtc in the cy14b104k is intended for permanently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the non-volatile elements when power was lost. during backup operation, the cy14b104k consumes 0.35 a (typical) at room temperature. the user must choose capacitor or battery values accord ing to the application. backup time values based on maximum current specifications are shown in the following table. nominal backup times are approximately two times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery is used, a 3 v lithium is recommended and the cy14b104k sources current only from the battery when the primary power is removed. however the battery is not recharged at any time by the cy14b104k. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. table 2. rtc backup time capacitor value backup time 0.1 f 72 hours 0.47 f 14 days 1.0 f 30 days [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 8 of 35 stopping and starting the oscillator the oscen bit in the calibration register at 0x7fff8 controls the enable and disable of the osc illator. this bit is non-volatile and is shipped to customers in th e enabled (set to ?0?) state. to preserve the battery life when the system is in storage, oscen must be set to ?1?. this turns off the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. while system power is off, if the voltage on the backup supply (v rtccap or v rtcbat ) falls below their respective minimum level, the oscillator may fail.the cy14b104k has the ability to detect oscillator failure when system power is restor ed. this is recorded in the oscillator fail bit (oscf) of the flags register at the address 0x7fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for enabled status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms, the oscf bit is set to ?1?. the system must check for this condition and then write ?0? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see setting the clock on page 7 ), which is the value last written to the time keeping registers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have been set when th e system was first powered on. to reset oscf, set the write bit ?w? (in the flags register at 0x7fff0) to a ?1? to enable writes to the flag register. write a ?0? to the oscf bit and then reset the write bit to ?0? to disable writes. calibrating the clock the rtc is driven by a quartz controlled crystal with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystals available in market typically have an error of + 20 ppm to + 35 ppm. however, cy14b104k employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25 c. this implies an error of +2.5 seconds to ?5 seconds per month. the calibration circuit adds or subt racts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibr ation register at 0x7fff8. the calibration bits occupy the five lo wer order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corresponds to an adjustment of 4.068 or ?2.034 ppm offset in oscillator error, depending on the sign. calibration occurs within a 64-minute cycl e. the first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64-minute cycle are modified. if a binary 6 is loaded, the first 12 are affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is, 4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. to determine the required calibration, the cal bit in the flags register (0x7fff0) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from the 512 hz indicates the degree and direction of the required correction. for example, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the write bit ?w? (in the flags register at 0x7fff0) to ?1? to enable writes to the flags register. write a value to cal, and then reset the write bit to ?0? to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the registers 0x7fff1?5) with the corresponding time of day and date values. when a match occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie) bit is set. there are four alarm match fields - date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x7fff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. to set, clear or enable an alarm, set the ?w? bit (in flags register - 0x7fff0) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. note cy14b104k requires the alarm match bit for seconds (0x7fff2?d7) to be set to ?0? for proper operation of alarm flag and interrupt. watchdog timer the watchdog timer is a free running down counter that uses the 32-hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a free running counter. on power-up, the watchdog time out value in register 0x7fff7 is loaded into the counter load register. counting begins on power-up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to the terminal value of ?0?. if the counter reaches this value, it causes an internal fl ag and an optional interrupt output. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 9 of 35 you can prevent the time out interrupt by setting wds bit to ?1? prior to the counter reaching ?0?. this causes the counter to reload with the watchdog time out value and to be restarted. as long as the user sets the wds bi t prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watchdog write bit to ?0?. when the wdw is ?0?, new writes to the watchdog time out value bits d5?d0 are enabled to modify the time out value. when wdw is ?1?, writes to bits d5?d0 are ignored. the wdw function enables a user to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 3 . note that setting the watchdog time out value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. if the watchdog interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared when user reads the flags registers. figure 3. watchdog timer block diagram . power monitor the cy14b104k provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to v switch threshold. as described in the section autostore operation on page 4 , when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the non-volatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write operations to nvsram are inhibited and the rtc functions are not available to the user. the rtc clock continues to operate in the background. the updated rtc time keeping registers data are available to the user after v cc is restored to the device (see autostore/power-up recall on page 22 ). interrupts the cy14b104k has flags register, interrupt register, and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by appropriate setting in the interrupt register (0x7fff6). in addition, each has an associated flag bit in the flags register (0x7fff0) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ?1?). after an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on int pin. these two bits are located in the interrupt register and can be us ed to drive level or pulse mode output from the int pin. in pulse mode, the pulse width is internally fixed at approximatel y 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags register is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. note cy14b104k generates valid interrupts only after the power-up recall sequence is comple ted. all events on int pin must be ignored for t hrecall duration after powerup. interrupt register watchdog interrupt enable (wie) : when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog time out occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register. alarm interrupt enable (aie) : when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in flags register. power fail interr upt enable (pfe) : when set to ?1?, the power fail monitor drives the pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in flags register. high/low (h/l) : when set to a ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to a ?0?, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to vcc by a 10 k resistor while using the interrupt in active low mode. pulse/level (p/l) : when set to a ?1? and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a ?0?, the int pin is driven high or low (determined by h/l) until the flags register is read. when an enabled interrupt source activates the int pin, an external host reads the flags r egisters to determine the cause. remember that all flags are cleared when the register is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to it s inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags register is read. if the int pin is used as a host reset, the flags register is not read during a reset. 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32,768 khz [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 10 of 35 flags register the flags register has three flag bits: wdf, af, and pf, which ca n be used to generate an interrupt. these flags are set by the watchdog timeout, alarm match, or powe r fail monitor respectively. the processor can either poll this register or enable interrupts when a flag is set. these flags are automatically reset when the register is read. the flags register is automatically loaded with the valu e 0x00 on power-up (except for the oscf bit. see stopping and starting the oscillator on page 8 ). figure 4. rtc recommended component configuration figure 5. interrupt block diagram recommended values y 1 = 32.768 khz (12.5 pf) c 1 = 12 pf c 2 = 69 pf note the recommended values for c1 and c2 include board trace capacitance. x out x in y1 c2 c1 wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable watchdog timer power monitor clock alarm vint wdf wie pf pfe af aie p/l pin driver h/l int v cc v ss [+] feedback
document #: 001-07103 rev. *u page 11 of 35 cy14b104k, cy14b104m table 3. rtc register map [9] register bcd format data [10] function/range cy14b104k cy14b104m d7 d6 d5 d4 d3 d2 d1 d0 0x7ffff 0x3ffff 10s years years years: 00?99 0x7fffe 0x3fffe 0 0 0 10s mo nths months months: 01?12 0x7fffd 0x3fffd 0 0 10s day of month d ay of month day of month: 01?31 0x7fffc 0x3fffc 0 0 0 0 0 day of week day of week: 01?07 0x7fffb 0x3fffb 0 0 10s hours hours hours: 00?23 0x7fffa 0x3fffa 0 10s minutes minutes minutes: 00?59 0x7fff9 0x3fff9 0 10s seconds seconds seconds: 00?59 0x7fff8 0x3fff8 oscen (0) 0 cal sign (0) calibration (00000) calibration values [11] 0x7fff7 0x3fff7 wds (0) wdw (0) wdt (000000) watchdog [11] 0x7fff6 0x3fff6 wie (0) aie (0) pfe (0) 0 h/l (1) p/l (0) 0 0 interrupts [11] 0x7fff5 0x3fff5 m (1) 0 10s alarm date al arm day alarm, day of month: 01?31 0x7fff4 0x3fff4 m (1) 0 10s alarm hours alarm hours alarm, hours: 00?23 0x7fff3 0x3fff3 m (1) 10s alarm minutes alarm minutes alarm, minutes: 00?59 0x7fff2 0x3fff2 m (1) 10s alarm seconds alarm, seconds alarm, seconds: 00?59 0x7fff1 0x3fff1 10s centuries centuries centuries: 00?99 0x7fff0 0x3fff0 wdf af pf oscf [12] 0 cal (0) w (0) r (0) flags [11] notes 9. upper byte d 15 ?d 8 (cy14b104m) of rtc registers are reserved for future use. 10. ( ) designates values shipped from the factory. 11. this is a binary value, not a bcd value. 12. when user resets oscf flag bit, the flags register will be updated after t rtcp time. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 12 of 35 table 4. register map detail register description cy14b104k cy14b104m 0x7ffff 0x3ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble oper ates from 0 to 9. the range for the register is 0?99. 0x7fffe 0x3fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibbl e (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains th e upper digit and operates from 0 to 1. the range for the register is 1?12. 0x7fffd 0x3fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) c ontains the 10s digit and operates from 0 to 3. the range for the register is 1?31. l eap years are automatically adjusted for. 0x7fffc 0x3fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that co rrelates to day of the week. day of the week is a ring counter that counts from 1 to 7 then return s to 1. the user must assign meaning to the day value, because the day is not integrated with the date. 0x7fffb 0x3fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x7fffa 0x3fffa time keepin g - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains th e upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x7fff9 0x3fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. the range for the register is 0?59. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 13 of 35 register description cy14b104k cy14b104m 0x7fff8 0x3fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to ?1?, the oscillator is stopped. when set to ?0 ?, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibrat ion adjustment is applied as an additi on (1) to or as a subtraction (0) from the time-base. calibration these five bits cont rol the calibration of the clock. 0x7fff7 0x3fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to ?1? reloads and restarts the watchdog timer. setting the bit to ?0? has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a ?0?. wdw watchdog write enable. setting this bit to 1 di sables any write to the watchdog timeout value (d5?d0). this allows the user to set the watc hdog strobe bit without dist urbing the timeout value. setting this bit to 0 allows bits d5?d0 to be writ ten to the watchdog regist er when the next write cycle is complete. this function is explained in more detail in watchdog timer on page 8 . wdt watchdog timeout selection. the watchdog timer in terval is selected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of ?1?) to 2 seconds (setting of 3 fh). setting the watchdog timer register to ?0? disables the timer. these bits c an be written only if the wdw bit was set to 0 on a previous cycle. 0x7fff6 0x3fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe 0 h/l p/l 0 0 wie watchdog interrupt enable. when set to ?1? and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to ?0?, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to ?1?, the al arm match drives the int pin and the af flag. when set to ?0?, the alarm matc h only affects the af flag. pfe power fail enable. when set to ?1?, the power fail monitor drives the int pin and the pf flag. when set to ?0?, the power fail moni tor affects only the pf flag. 0 reserved for future use h/l high/low. when set to ?1?, the int pin is driven active high. when set to ?0,? the int pin is open drain, active low. p/l pulse/level. when set to 1, the int pin is driv en active (determined by h/l) by an interrupt source for approximately 200 ms. when set to 0, the int pin is driven to an active level (as set by h/l) until the flags register is read. 0x7fff5 0x3fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. when this bit is set to ?0?, the date value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the date value. table 4. register map detail (continued) [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 14 of 35 register description cy14b104k cy14b104m 0x7fff4 0x3fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to ?0?, the hours value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the hours value. 0x7fff3 0x3fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. m match. when this bit is set to ?0 ?, the minutes value is used in t he alarm match. setting this bit to ?1? causes the match circuit to ignore the minutes value. 0x7fff2 0x3fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or deselect the seconds? value. m match. when this bit is set to ?0,? the seconds value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the seconds value. 0x7fff1 0x3fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. the range for the register is 0-99 centuries. 0x7fff0 0x3fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read only bit is set to ?1? when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags register is read or on power-up af alarm flag. this read only bit is set to ?1? when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags register is read or on power-up. pf power fail flag. this read only bit is set to ?1? when power falls below the power fail threshold v switch . it is cleared to 0 when the flags register is read or on power-up. oscf oscillator fail flag. set to ?1? on power-up if t he oscillator is enabled and not running in the first 5 ms of operation. this indicates that rtc backup power failed and clock value is no longer valid. this bit survives the power cycle an d is never cleared inte rnally by the chip. the user must check for this condition and write '0' to clear this flag. when user resets oscf flag bit, the bit will be updated after t rtcp time. cal calibration mode. when set to ?1?, a 512 hz s quare wave is output on the int pin. when set to ?0?, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power-up. w write enable: setting the ?w? bit to ?1? freezes updates of the rt c registers. the user can then write to rtc registers, alarm registers, calibrati on register, interrupt register and flags register. setting the ?w? bit to ?0? causes the contents of the rtc registers to be transferred to the time keeping counters if the time has changed. this transfer process takes t rtcp time to complete. this bit defaults to 0 on power-up. r read enable: setting ?r? bit to ?1?, stops clock updates to user rtc registers so that clock updates are not seen during the reading process. set ?r? bit to ?0? to resume clock updates to the holding register. setting this bit does not require ?w? bit to be set to ?1?. this bit defaults to 0 on power-up. table 4. register map detail (continued) [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 15 of 35 best practices nvsram products have been used effectively for over 27 years. while ease-of-use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the non-volatile cells in this nvsram product are delivered from cypress with 0x00 written in all cells. incoming inspection routines at customer or c ontract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power-up boot firmware routines should rewrite the nvsram into the desired state (for example, autostore enabled). while the nvsram is shipped in a pres et state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this maximum v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. when base time is updated, th ese updates are transferred to the time keeping registers when ?w? bit is set to ?0?. this transfer takes t rtcp time to complete. it is recommended to initiate software store or hardware store after t rtcp time to save the base time into non-volatile memory. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 16 of 35 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time at 150 ? c ambient temperature ................................. 1000 h at 85 ? c ambient temperature ................................ 20 years ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +150 ? c supply voltage on v cc relative to v ss ...........?0.5 v to 4.1 v voltage applied to outputs in high z state .................................... ?0.5 v to v cc + 0.5 v input voltage ....................................... ?0.5 v to v cc + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current..................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range (v cc = 2.7 v to 3.6 v) parameter description test conditions min typ [13] max unit v cc power supply 2.7 3.0 3.6 v i cc1 average v cc current t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) ??70 52 ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc(typ) , 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?35?ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??5ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). w bit set to ?0?. standby current level after non-volatile cycle is complete. inputs are static. f = 0 mhz. ??5ma i ix [14] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 ? +1 ? a input leakage current (for hsb )v cc = max, v ss < v in < v cc ?100 ? +1 ? a i oz off state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 ? +1 ? a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v v cap [15] storage capacitor between v cap pin and v ss , 5 v rated 61 68 180 ? f notes 13. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 14. the hsb pin has i out = ?2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. 15. min v cap value guarantees that there is a sufficient charge ava ilable to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within t he specified min and max limits. refer application note an43593 for more details on v cap options. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 17 of 35 ac test conditions input pulse levels....................................................0 v to 3 v input rise and fall times (10%?90%)............................ < 3 ns input and output timing reference levels........................ 1.5 v data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c non-volatile store operations 1,000 k capacitance parameter [16] description test conditions max unit c in input capacitance (except bhe , ble and hsb ) t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 7pf input capacitance (for bhe , ble and hsb ) 8pf c out output capacitance (except hsb ) 7 pf output capacitance (for hsb ) 8 pf thermal resistance parameter [16] description test conditions 44-pin tsop ii 54-pin tsop ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 43.3 42.03 ? c/w ? jc thermal resistance (junction to case) 5.56 6.08 ? c/w ac test loads figure 6. ac test loads 3.0 v output 5 pf r1 r2 789 ? 3.0 v output 30 pf r1 r2 789 ? 577 ? 577 ? 16. these parameters are only guaranteed by design and are not tested. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 18 of 35 rtc characteristics over the operating range parameters description min typ [17] max units v rtcbat rtc battery pin voltage 1.8 3.0 3.6 v i bak [18] rtc backup current t a (min) ? ? 0.35 ? a 25 c ? 0.35 ? ? a t a (max) ? ? 0.5 ? a v rtccap [19] rtc capacitor pin voltage t a (min) 1.6 ? 3.6 v 25 c 1.5 3.0 3.6 v t a (max) 1.4 ? 3.6 v tocs rtc oscillator time to start ? 1 2 sec t rtcp rtc processing time from end of ?w? bit set to ?0? ? ? 350 ? s r bkchg rtc backup capacitor charge current-limiting resistor 350 ? 850 ? notes 17. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 18. from either v rtccap or v rtcbat . 19. if v rtccap > 0.5 v or if no capacitor is connected to v rtccap pin, the oscillator starts in t ocs time. if a backup capacitor is connected and v rtccap < 0.5 v, the capacitor must be allowed to charge to 0.5 v for oscillator to start. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 19 of 35 ac switching characteristics over the operating range parameters [20] description 25 ns 45 ns unit cypress parameter alt parameter min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 45 ns t rc [21] t rc read cycle time 25 ? 45 ? ns t aa [22] t aa address access time ? 25 ? 45 ns t doe t oe output enable to data valid ? 12 ? 20 ns t oha [22] t oh output hold after address change 3 ? 3 ? ns t lzce [23, 24] t lz chip enable to output active 3 ? 3 ? ns t hzce [23, 24] t hz chip disable to output inactive ? 10 ? 15 ns t lzoe [23, 24] t olz output enable to output active 0 ? 0 ? ns t hzoe [23, 24] t ohz output disable to output inactive ? 10 ? 15 ns t pu [23] t pa chip enable to power active 0 ? 0 ? ns t pd [23] t ps chip disable to power standby ? 25 ? 45 ns t dbe ? byte enable to data valid ? 12 ? 20 ns t lzbe [23] ? byte enable to output active 0 ? 0 ? ns t hzbe [23] ? byte disable to output inactive ? 10 ? 15 ns sram write cycle t wc t wc write cycle time 25 ? 45 ? ns t pwe t wp write pulse width 20 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 30 ? ns t sd t dw data setup to end of write 10 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? ns t hzwe [23, 24, 25] t wz write enable to output disable ? 10 ? 15 ns t lzwe [23, 24] t ow output active after end of write 3 ? 3 ? ns t bw ? byte enable to end of write 20 ? 30 ? ns switching waveforms figure 7. sram read cycle 1 (address controlled) [21, 22, 26] address data output address valid previous data valid output data valid t rc t aa t oha notes 20. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and load capacitance shown in figure 6 on page 17 . 21. we must be high during sram read cycles. 22. device is continuously selected with ce , oe and bhe / ble low. 23. these parameters are only guaranteed by design and are not tested. 24. measured 200 mv from steady state output voltage. 25. if we is low when ce goes low, the outputs remain in the high impedance state. 26. hsb must remain high duri ng read and write cycles. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 20 of 35 figure 8. sram read cycle 2 (ce and oe controlled) [27, 28, 29] figure 9. sram write cycle 1 (we controlled) [27, 29, 30, 31] switching waveforms (continued) address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce notes 27. bhe and ble are applicable for 16 configuration only. 28. we must be high during sram read cycles. 29. hsb must remain high during read and write cycles. 30. if we is low when ce goes low, the outputs remain in the high impedance state. 31. ce or we must be ?? v ih during address transitions. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 21 of 35 figure 10. sram write cycle 2 (ce controlled) [32, 33, 34, 35] figure 11. sram write cycle 3 (bhe and ble controlled) [33, 34, 35, 36, 37] switching waveforms (continued) data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe (not applicable for rtc register writes) notes 32. bhe and ble are applicable for 16 configuration only. 33. if we is low when ce goes low, the outputs remain in the high impedance state. 34. hsb must remain high during read and write cycles. 35. ce or we must be ?? v ih during address transitions. 36. while there are 19 address lines on the cy14b104k (18 address lines on the cy14b104m), only 13 address lines (a 14 ?a 2 ) are used to control software modes. the remaining address lines are don?t care. 37. only ce and we controlled writes to rtc registers are allowed. ble pin must be held low before ce or we pin goes low for writes to rtc register. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 22 of 35 autostore/power-up recall over the operating range parameter description cy14b104k/cy14b104m unit min max t hrecall [38] power-up recall duration ? 20 ms t store [39] store cycle duration ? 8 ms t delay [40] time allowed to complete sram write cycle ? 25 ns v switch low-voltage trigger level ? 2.65 v t vccrise [41] v cc rise time 150 ? ? s v hdis [41] hsb output disable voltage ? 1.9 v t lzhsb [41] hsb to output active time ? 5 ? s t hhhd [41] hsb high active time ? 500 ns switching waveforms figure 12. autostor e or power-up recall [42] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 39 39 43 43 notes 38. t hrecall starts from the time v cc rises above v switch . 39. if an sram write has not taken place since the last non-vo latile cycle, no autostore or hardware store takes place. 40. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 41. these parameters are only guaranteed by design and are not tested. 42. read and write cycles are ignored during store, recall, and while v cc is below v switch . 43. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 23 of 35 software controlled store and recall cycle over the operating range parameter [44, 45] description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 ? 45 ? ns t sa address setup time 0 ? 0 ? ns t cw clock pulse width 20 ? 30 ? ns t ha address hold time 0 ? 0 ? ns t recall recall duration ? 200 ? 200 ? s t ss [46, 47] soft sequence processing time ? 100 ? 100 ? s switching waveforms figure 13. ce and oe controlled software store and recall cycle [45] figure 14. autostore enable and disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note 48 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note 48 notes 44. the software sequence is clocked with ce controlled or oe controlled reads. 45. the six consecutive addresses must be read in the order listed in table 1 . we must be high during all six consecutive cycles. 46. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 47. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. 48. dq output data at the sixth read may be invalid since the output is disabled at t delay time. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 24 of 35 hardware store cycle over the operating range parameter description cy14b104k/cy14b104m unit min max t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns switching waveforms figure 15. hardware store cycle [49] figure 16. soft sequence processing [50, 51] t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v c c only by internal sram is disabled as long as hsb (in) is driven low . hsb driver is disabled t dhsb 100 kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 49. if an sram write has not taken place since the last non-volatile cycle, no autostore or hardware store takes place. 50. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 51. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 25 of 35 truth table for sram operations hsb should remain high for sram operations. table 5. truth table for 8 configuration ce we oe inputs and outputs [52] mode power h x x high z deselect/power-down standby l h l data out (dq 0 ?dq 7 ) read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ) write active table 6. truth table for 16 configuration ce we oe bhe [53] ble [53] inputs and outputs [52] mode power h x x x x high z deselect/power-down standby l x x h h high z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z read active l h l l h data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z read active l h h l l high z output disabled active l h h h l high z output disabled active l h h l h high z output disabled active llxlldata in (dq 0 ?dq 15 ) write active llxhldata in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z write active llxlhdata in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z write active notes 52. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 53. bhe and ble are applicable for 16 configuration only. [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 26 of 35 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b104k-zs25xit 51-85087 44-pin tsop ii industrial cy14b104k-zs25xi 51-85187 44-pin tsop ii cy14b104m-zsp25xit 51-85160 54-pin tsop ii cy14b104m-zsp25xi 51-85160 54-pin tsop ii 45 CY14B104K-ZS45XIt 51-85087 44-pin tsop ii CY14B104K-ZS45XI 51-85187 44-pin tsop ii cy14b104m-zsp45xit 51-85160 54-pin tsop ii cy14b104m-zsp45xi 51-85160 54-pin tsop ii all the above parts are pb-free. option: t - tape & reel blank - std. speed: 25 - 25 ns data bus: k - 8 + rtc m - 16 + rtc density: 104 - 4 mb voltage: b - 3.0 v cypress cy14 b 104 k - zsp 25 x i t nvsram 14 - temperature: i - industrial (?40 to 85 c) pb-free package: zsp - 44-pin tsop ii 45 - 45 ns zsp - 54-pin tsop ii [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 27 of 35 package diagrams figure 17. 44-pin tsop ii, 51-85087 51-85087 *c [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 28 of 35 figure 18. 54-pin tsop ii (22.4 11.84 1.0 mm), 51-85160 package diagrams (continued) 51-85160 *a [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 29 of 35 acronyms document conventions units of measure acronym description bcd binary coded decimal bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance hsb hardware store busy i/o input/output nvsram non-volatile static random access memory oe output enable rohs restriction of hazardous substances rtc real time clock rwi read and write inhibited sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius f farads hz hertz khz kilo hertz k ? kilo ohms mhz mega hertz ? a micro amperes ma milli amperes ? f micro farads ? s micro seconds ms milli seconds ns nano seconds ? ohms % percent pf pico farads ppm parts per million v volts w watts [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 30 of 35 document history page document title: cy14b104k/cy14b104m, 4-mbit (512 k 8/256 k 16) nvsram with real time clock document number: 001-07103 rev. ecn no. orig. of change submission date description of change ** 431039 tup see ecn new data sheet *a 489096 tup see ecn removed 48 ssop package added 44 tsopii and 54 tsopii packages updated part numbering nomenclature and ordering information added soft sequence processing time waveform added rtc characteristics table added rtc recommended component configuration *b 499597 pci see ecn removed 35ns speed bin added 55ns speed bin. updated ac table for the same changed ?unlimited? read/write to ?infinite? read/write features section: changed typical i cc at 200-ns cycle time to 8 ma changed store cycles from 500k to 200k cycles. shaded commercial grade in operating range table. modified icc/isb specs. changed v cap value in dc table added 44 tsop ii in thermal resistance table modified part nomenclature table. chan ges reflected in the ordering informa- tion table. *c 517793 tup see ecn removed 55ns speed bin changed pinout for 44tsopii and 54tsopii packages changed i sb to 1ma changed i cc4 to 3ma changed v cap min to 35 ? f changed v ih max to v cc + 0.5v changed t store to 15ns changed t pwe to 10ns changed t sce to 15ns changed t sd to 5ns changed t aw to 10ns removed t hlbl added timing parameters for bhe and ble - t dbe , t lzbe , t hzbe , t bw removed min. specification for vswitch changed t glax to 1ns added t delay max. of 70us changed t ss specification from 70us min. to 70us max. *d 825240 uha see ecn changed the data sheet from advance information to preliminary changed t dbe to 10ns in 15ns part changed t hzbe in 15ns part to 7ns and in 25ns part to10ns changed t bw in 15ns part to 15ns and in 25ns part to 20ns changed t glax to t ghax changed the value of i cc3 to 25ma changed the value of t aw in 15ns part to 15ns *e 914280 uha see ecn changed the figure-14 title from 54-pb to 54 pin included all the information for 45ns part in this data sheet [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 31 of 35 *f 1890926 vsutmp8 / aesa see ecn added footnote 1, 2 and 3. updated logic block diagram updated pin definition table changed 8mb address expansion pin from pin 43 to pin 42 for 44-tsop ii (x8) package. corrected typo in v il min spec changed the value of i cc3 from 25ma to 13ma changed i sb value from 1ma to 2ma updated ordering information table rearranging of footnotes. changed package diagrams title. the pins x1 and x2 interchanged in 44tsop ii(x8) and 54tsop ii(x16) pinout diagram. *g 2267286 gvch / pyrs see ecn rearranging of ?features? added bhe and ble information in pi n definitions table updated figure 2 (autostore mode) updated footnote 6 rtc register map:register 0x1fff6:changed d4 from abe to 0 register map detail:0x1f ff6:changed d4 from abe to 0 and removed abe information changed i cc2 & i cc4 from 3ma to 6ma changed i cc3 from 13ma to 15ma changed i sb from 2ma to 3ma added input leakage current (i ix ) for hsb in dc electrical characteristics table changed vcap from 35uf min and 57uf max value to 54uf min and 82uf max value corrected typo in t dbe value from 22ns to 20ns for 45ns part corrected typo in t hzbe value from 22ns to 15ns for 45ns part corrected typo in t aw value from 15ns to 10ns for 15ns part changed vrtccap max from 2.7v to 3.6v changed trecall from 100 to 200us added footnote 10, 29 reframed footnote 18, 25 added footnote 18 to figure 8 (sram write cycle #1) added footnote 18, 26 and 27 to figure 9 (sram write cycle #2) *h 2483627 gvch / pyrs see ecn removed 8 ma typical i cc at 200 ns cycle time in feature section referenced footnote 9 to i cc3 in dc characteristics table changed i cc3 from 15 ma to 35 ma changed vcap minimum value from 54 uf to 61 uf changed t avav to t rc changed v rtccap minimum value from 1.2v to 1.5v figure 12:changed t sa to t as and t sce to t cw *i 2519319 gvch / pyrs 06/20/08 added 20 ns access speed in ?features? added i cc1 for trc=20 ns for both industri al and commercial temperature grade updated thermal resistance values for 44-tsop ii and 54-tsop ii packages added ac switching characteristi cs specs for 20 ns access speed added software controlled store/re call cycle specs for 20 ns access speed updated ordering information and part numbering nomenclature document history page (continued) document title: cy14b104k/cy14b104m, 4-mbit (512 k 8/256 k 16) nvsram with real time clock document number: 001-07103 rev. ecn no. orig. of change submission date description of change [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 32 of 35 *j 2600941 gvch / pyrs 11/04/08 removed 15 ns access speed from ?features? changed part number from cy14b104k/cy14b104m to cy14b104ka/cy14b104ma updated logic block diagram updated footnote 1 added footnote 2 pin definition: updated we , hsb and nc pin description page 4: updated sram read, sram write, autostore operation descrip- tion page 4: updated hardware store op eration and hardware recall (pow- er-up) description footnote 1 and 8 referenced for mode selection table updated footnote 6 page 6: updated data protection description page 6: updated starting and stopping the oscillator description page 7: updated calibrating the clock description page 7: updated alarm description page 8: added flags register added footnote 10 and 11 updated figure 4: removed rf register and changed c 2 value from 56pf to 12pf updated register map table 3 updated register map detail table 4 maximum ratings: added max. accumulated storage time changed output short circuit current parameter name to dc output current changed i cc2 from 6ma to 10ma changed i cc4 from 6ma to 5ma changed i sb from 3ma to 5ma updated i cc1, i cc3, i sb and i oz test conditions changed v cap voltage max value from 82uf to 180uf updated footnote 12 and 13 added footnote 14 added data retention and endurance table updated input rise and fall time in ac test conditions changed tocs value for minimum temperature from 10 to 2 sec updated tocs value for room temperature from 5 to 1sec referenced footnote 20 to t oha parameter updated all switching waveforms updated footnote 20 added figure 11 (sram write cycle:bhe and ble controlled) updated t delay value added v hdis , t hhhd and t lzhsb parameters updated footnote 27 added footnote 29 software controlled store/recall table: changed t as to t sa changed t ghax to t ha changed t ha value from 1ns to 1ns added t dhsb parameter changed t hlhx to t phsb updated t ss from 70us to 100us added truth table for sram operations updated ordering information a nd part numbering nomenclature document history page (continued) document title: cy14b104k/cy14b104m, 4-mbit (512 k 8/256 k 16) nvsram with real time clock document number: 001-07103 rev. ecn no. orig. of change submission date description of change [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 33 of 35 *k 2653928 gvch / pyrs 02/04/09 changed part number fr om cy14b104ka/cy14b104ma to cy14b104k/cy14b104m updated real time clock operation description added factory default values to register map table 3 added footnote 9 updated flag register description in table 4 updated c1, c2 values to 21pf, 21pf respectively changed i bak value from 350 na to 450 na at hot temperature changed v rtccap typical value from 2.4v to 3.0v referenced note 15 to parameters t lzce , t hzce , t lzoe, t hzoe, t lzbe, t lzwe, t hzwe and t hzbe added footnote 22 updated figure 13 *l 2710240 gvch / pyrs 05/22/09 moved data sheet status from preliminary to final changed pin names x 1 , x 2 to x out , x in respectively. updated autostore operation updated c1, c2 values to 12pf, 69pf from 21pf, 21pf respectively updated i sb test condition updated footnote 11 updated i bak and v rtccap parameter values added r bkchg parameter to rtc characteristics table added footnote 15 referenced footnote 13 to v ccrise , t hhhd and t lzhsb parameters updated v hdis parameter description *m 2738586 gvch 07/15/09 page 4: updated hardware store (hsb ) operation description page 4: updated software store description added best practices updated t delay parameter description updated footnote 25 and added footnote 32 referenced footnote 32 to figure 13 and figure 14 *n 2758397 gvch / aesa 09/01/09 removed commercial temp erature related specifications removed 20 ns access speed related specs changed v rtcbat max value from 3.3v to 3.6v changed r bkchg min value from 450 ?? to 350 ? updated footnote 15 *o 2826364 gvch / pyrs 12/11/09 changed store cycles to quan tumtrap from 200k to 1 million updated i bak rtc backup current spec unit from na to ? a *p 2858300 gvch 01/19/2010 added contents. *q 2923475 gvch / aesa 04/27/2010 table 1 : added more clarity on hsb pin operation hardware store (hsb) operation : added more clarity on hsb pin operation table 1 : added more clarity on bhe /ble pin operation updated hsb pin operation in figure 12 updated footnote 27 updated package diagrams *r 3132368 gvch 01/10/2011 updated setting the clock description added footnote 12 updated w bit description in register map detail table updated best practices updated input capacitance for bhe and ble pin updated input and output capacitance for hsb pin added t rtcp parameter to rtc characteristics table figure 12 : typo error fixed added acronyms table and document conventions table *s 3150253 gvch 01/21/2011 no technical updates document history page (continued) document title: cy14b104k/cy14b104m, 4-mbit (512 k 8/256 k 16) nvsram with real time clock document number: 001-07103 rev. ecn no. orig. of change submission date description of change [+] feedback
cy14b104k, cy14b104m document #: 001-07103 rev. *u page 34 of 35 *t 3208661 gvch 03/29/2011 updated thermal resistance values for all packages *u 3305495 gvch 07/07/2011 updated dc electrical characteristics (added note 15 and referred the same note in v cap parameter). updated ac switching characteristics (added note 20 and referred the same note in parameters). document history page (continued) document title: cy14b104k/cy14b104m, 4-mbit (512 k 8/256 k 16) nvsram with real time clock document number: 001-07103 rev. ecn no. orig. of change submission date description of change [+] feedback
document #: 001-07103 rev. *u revised july 12, 2011 page 35 of 35 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14b104k, cy14b104m ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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